1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a technique for adjusting a capacitance of a bit line in a read operation.
2. Description of the Background Art
A read operation of a conventional semiconductor memory device shown in FIGS. 3 and 4 of Japanese Laid-Open Patent Publication No. 2005-228446 will be outlined below.
The conventional semiconductor memory device includes a plurality of memory cells and a reference cell.
A certain amount of current flows through a memory cell that has been selected as a cell to be read, and the amount of current depends on whether data stored therein is “1” or “0”. Therefore, the potential of a main bit line connected to a memory cell being read also depends on whether data stored in the memory cell is “0” or “1”.
The reference cell is designed so that an intermediate amount of current flows through the reference cell, wherein the intermediate amount of current is between the amount of current that flows through a memory cell storing “1” therein and the amount of current that flows through a memory cell storing “0” therein. An intermediate potential is produced along a complementary main bit line connected to a reference cell in a read operation, wherein the intermediate potential is between the potential produced along a main bit line connected to a memory cell storing “0” and that produced along a main bit line connected to a memory cell storing “1”.
Then, the potential along the main bit line to which the memory cell is connected and the potential along the complementary main bit line to which the reference cell is connected are amplified by a sense amplifier.
It is preferred that the total parasitic capacitance of the main bit line to which the memory cell is connected and that of the complementary main bit line to which the reference cell is connected are equal to each other. If the parasitic capacitances are different from each other, the amount of delay since the selection of a memory cell until a potential according to the data stored therein is produced along a main bit line connected to the memory cell will be different from the amount of delay since the selection of a reference cell until the intermediate potential is produced along a complementary main bit line connected to the reference cell. As a result, data will not be read accurately.
With the conventional semiconductor memory device, in order to balance the parasitic capacitance, a sub-bit line of a sector different from a sector including a memory cell being read is connected to a complementary main bit line that is connected to the reference cell. For example, when data is read out from a memory cell MC00 of the sector 0, a sub-bit line DBL1c of the sector 1, in addition to a sub-bit line RDBL0c, is connected to a complementary main bit line MBLc that is connected to a reference cell RC0n. In FIG. 4 of the above-identified patent document, the parasitic capacitance C1 and the parasitic capacitance C4 are substantially equal to each other, and the parasitic capacitance C3 and the parasitic capacitance C2 are substantially equal to each other, with the parasitic capacitance C9 being small. Therefore, the total parasitic capacitance C1+C3 of the main bit line MBLa and the total parasitic capacitance C4+C9+C2 of the complementary main bit line MBLc are substantially equal to each other.
Japanese Laid-Open Patent Publication No. 2004-110872 discloses a technique for coupling a load capacitance according to the address of the memory cell being read to a bit line that is connected to the reference cell.
Japanese Laid-Open Patent Publication No. 2001-307494 discloses a technique in which a reference load circuit is provided for each of a plurality of blocks each including a memory cell array, whereby the same load is applied to the reference signal as that applied to data being read out from the memory cell array.
However, with the semiconductor memory device shown in FIGS. 3 and 4 of Japanese Laid-Open Patent Publication No. 2005-228446, when the parasitic capacitance of the sub-bit line connected to the reference cell is large, the difference between the total parasitic capacitance of the main bit line and that of the complementary main bit line is large. For example, in the above case where data is read out from a memory cell MC00 of the sector 0, if the parasitic capacitance C9 of the sub-bit line RDBL0c connected to the reference cell is large, the difference between the total parasitic capacitance C1+C3 of the main bit line MBLa and the total parasitic capacitance C4+C9+C2 of the complementary main bit line MBLc is large. If the difference between the total parasitic capacitance of the main bit line to which the memory cell is connected and that of the complementary main bit line to which the reference cell is connected is large, data cannot be read accurately.
This problem does not occur if the parasitic capacitance of the sub-bit line, which is connected to the complementary main bit line in order to balance the total parasitic capacitance, is made smaller than the parasitic capacitance of the sub-bit line, which is connected to the memory cell being read, by the parasitic capacitance of the sub-bit line connected to the reference cell. However, the number of word lines of the sector including the sub-bit line, which is connected to the complementary main bit line in order to balance the total parasitic capacitance, will then be an undesirable odd number, which will be inconvenient and impractical to users who use the semiconductor memory device.